The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to methods and apparatus for etching through an IC's layer stack, including the metallization layer, during IC fabrication.
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are etched from a metallization layer disposed above the wafer, are then employed to couple the devices together to form the desired circuit. To facilitate discussion, FIG. 1 illustrates a cross-sectional view of a layer stack 20, representing the layers formed during the fabrication of a typical semiconductor IC. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 20, there is shown a wafer 100. An oxide layer 102, typically comprising SiO.sub.2, is formed above wafer 100. A barrier layer 104, typically formed of Ti, TiW, TiN or other suitable barrier materials, may be disposed between oxide layer 102 and a subsequently deposited metallization layer 106. Barrier layer 104, when provided, functions to prevent the diffusion of silicon atoms from oxide layer 102 into the metallization layer.
Metallization layer 106 typically comprises copper, aluminum or one of the known aluminum alloys such as Al--Cu, Al--Si, or Al--Cu--Si. For convenience, the metallization layer 106 is referred to herein as the aluminum layer although it should be understood that such a reference may include a layer consisting of any of the aforementioned aluminum alloys. The remaining two layers of FIG. 1, i.e., an anti-reflective coating (ARC) layer 108 and an overlaying photoresist (PR) layer 110, are then formed atop metallization layer 106. The ARC layer 108, typically comprising TiN or TiW, helps prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the metallization layer 106 and may, in some cases, inhibit hillock growth. Photoresist layer 110 represents a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultra-violet rays. The layers of layer stack 20 are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To form the aforementioned metallic interconnect lines, a portion of the layers of the layer stack, including the metallization layer, e.g., metallization layer 106, are etched using a suitable photoresist technique. By way of example, one such photoresist technique involves the patterning of photoresist layer 110 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of the metallization layer that are unprotected by the mask are then etched away, leaving behind metallization interconnect lines or features.
For illustrative purposes, FIG. 2 shows a cross-sectional view of layer stack 20 of FIG. 1 after conventional etching is completed. In this example, the metallic interconnect lines are represented by the unetched portions of metallization layer 106.
To achieve greater circuit density, modem IC circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased. By way of example, while a line width of approximately 0.8 microns (.mu.m) is considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) IC, 256 Mb DRAM IC's preferably employ interconnect lines as thin as 0.25 microns or even thinner.
As the feature sizes shrink, it becomes increasingly difficult to achieve a uniform etch rate across the wafer. Typically, the etch rate in the narrow spacings is slower than that in wider trenches or open field regions. This phenomenon, referred herein as the loading in etch rates, may be a consequence of microloading and/or aspect ratio dependent etching (ARDE). Microloading refers primarily to the situation wherein the etch rate is smaller in areas where there is a high density of line spacings relative to the etch rate of identically sized trenches located in a less dense area. ARDE, on the other hand, refers primarily to the situation wherein variations in etch rates are observed among trenches that are located in areas of similar trench density and among trenches that have different aspect ratios. The loading in etch rates causes trenches to be formed in the layer stack at different rates. The loading in etch rates becomes more severe when trench widths fall below about 0.8 microns, and especially when trench widths fall below about 0.35 microns. As a result of the etch rate variations, by the time metal etching is complete in areas having a slow etch rate (e.g., in the narrower line spacings), overetching, i.e., the inadvertent removal of materials from underlying layers, may have already occurred in areas having a higher etch rate (e.g., the open field regions).
With reference to FIG. 2, area 120 represents an open field region where the metallization layer is overetched (by distance d1 or d3). Area 122 represents the region where the etch rate loading has the potential to occur. The metallization at the bottom of the trench is underetched by distance .DELTA.X.sub.n (or X.sub.0 -d.sub.2). If the etch rate variations are sufficiently large, it may not be possible, for some geometry, to etch though the target layer, e.g., the metal layer, in the narrower spacings before undue damage to the underlying layers in the open field regions occurs. For example, large etch rate variations may cause undue overetching and excessive oxide loss in area 120, rendering the wafer undergoing processing unsuitable for use in IC fabrication.
In view of the foregoing, what is desired is improved methods and apparatus for minimizing the loading in etch rates in the etching of the layer stack.